Selected solution(s) will be trialled in pilot studies, with the possibility of further adoption upon successful trials, co-developed with the challenge holder. Funding of up to £80,000 is available per single successful organisation  

All organisations associated with national security undertake sensitive and classified daily tasks, and there is the invariable need to use electronic equipment. Sensitive equipment may be sourced from a range of suppliers varying from bespoke construction by HMGCC to less well-established third-party routes. With all routes, there is a requirement to conduct due diligence on the constituent parts of an electronic system &ndash; ensuring functionality and security.
The focus of this challenge is to non-destructively image and verify printed circuit boards (PCB), specifically focusing on analysing copper traces through both the external and internal stack-up layers of complex multi-layer FR4 PCBs.

The Challenge

There exists capability to assure how a PCB functions and compare this to the intended design, or perhaps where there is no accessible design file. Displayed in table 1 is a non-exhaustive list of methods, the reason to use them and their drawbacks.
Table 1. Gap analysis.

The gap

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A PCB for verification could consist of multiple (potentially 10 or more) layers of copper traces, bonded on to FR4 glass epoxy substrates and laminated together. Each copper trace could be less than 35um in height, less than 100um in width and a copper clad layer less than 150um thick. On each PCB would be assembled a variety of electronic components of varying sizes and densities.
The variations in density and size of placed electronic components, thickness of the PCB, multiple copper trace layers and small feature sizes makes it very challenging to image copper traces on internal layers. Density variations will also likely cause shadowing across the imaged copper&nbsp;traces and whatever novel imaging method or technique is proposed, the capability to interpret this imperfect imagery to verify the copper trace routing and features is a requirement.
To scale PCB assurance capability on high value equipment that must be usable after examination, requires development of non-destructive and novel methods to image and interpret the images of copper traces throughout complex multilayer PCBs to quickly assure that only intended functionality and connections are present, while retaining a low barrier to entry of use for the analyst.

A national security organisation is about to launch 10 new products in support of critical operational work. These products are portable, complex pieces of electronic equipment.
This equipment has been produced through collaboration including national security engineering specialists who have the full context of the project, trusted industrial partners who are aware of engineering requirements, and subcontracted third parties working on specific parts of the development. Thorough review of design and components helps provide appropriate assurance.
Kate, an assurance engineer, leads a team to review delivered hardware, testing each of the 10 products and every single item prior to their use by national security customers.
This used to be a mammoth task and not always possible with the complexity of multi-layer FR4 based PCBs. But, by using the newly developed non-destructive PCB verification machine, the team can cycle through each device rapidly. Added to this, it is easy to use and requires minimal training of staff.
Where a design file is present against which to compare the PCB images, the machine images the copper traces throughout the PCB stack-up and identifies the components to build a representative CAD/electronic design specification and compares this to the design file. The software also automatically flags if there are anomalies against the original design files, for further investigation.
In situations where a design file is not available, the machine uses artificial intelligence (AI) weightings to segment the individual images across the various FR4 layers to effectively &lsquo;build&rsquo; a design file. The AI determines the probability of each image segment being from the same (or different) layer on the PCB, and groups these segments together to extract the copper trace routing on and between layers. This approach of probabilistically grouping the image segments so that they are provisionally assigned as belonging to a PCB layer helps with removing image artifacts in the AI-derived design file, such as the &lsquo;shadowing&rsquo; sometimes seen from a CT scan.
Once each product has been analysed, Kate&rsquo;s team can confirm the delivered hardware meets the same specification as the design file.

Example use case

Proposals should be focused on a proof of concept at Technology Readiness Level (TRL) 2-4, to be demonstrated towards the end of the five- month project, with a view to further development in future phases of work.
Desirable functions:
<ul>
<li>Method can image copper traces throughout multi-layered FR4 based PCBs.</li>
<li>Method works around possible shadowing or blocking effect from attached components.</li>
<li>Machine vision and machine learning processes to interpret images.</li>
<li>Direct and easy comparison of imaged PCB against original design files.</li>
<li>Easy to use and minimal training required.</li>
<li>Reasonably fast process (less than one day per PCB).</li>
<li>Equipment must be useable within a normal lab setting, i.e. not be prohibitively large or hazardous.</li>
</ul>
What we don&rsquo;t want:
<ul>
<li>Horizon scanning</li>
<li>Report of theoretical techniques</li>
<li>Technology available more than 5 years from now</li>
</ul>

Project scope

Competition opens: Monday 15 July 2024
Deadline for questions: Tuesday 13 August 2024
Clarifying questions published: Tuesday 20 August 2024
Competition closes: Thursday 29 August 2024 at 5:00pm
Applicant notified: Monday 9 September 2024
Pitch day in Milton Keynes: Tuesday 17 September 2024
Target project kick-off: Monday 21 October 2024

Dates

This challenge is open to sole innovators, industry, academic and research organisations of all types and sizes. There is no requirement for security clearances.
Solution providers or direct collaboration from <a href="https://www.gov.uk/guidance/current-arms-embargoes-and-other-restrictions">countries listed by the UK government under trade sanctions and/or arms embargoes</a>, are not eligible for HMGCC Co-Creation challenges.

Eligibility

All proposals, regardless of the application route, will be assessed by the HMGCC Co-Creation team. Proposals will be scored 1&ndash;5 on the following criteria:
Scope: Does the proposal fit within the challenge scope, taking into consideration cost and benefit?
Innovation: Is the technical solution credible, will it create new knowledge and IP, or use existing IP?
Deliverables: Will the proposal deliver a full or partial solution, if a partial solution, are there collaborations identified?
Timescale: Will the proposal deliver a <a href="https://www.gartner.com/en/marketing/glossary/minimum-viable-product-mvp-">minimum viable product</a> within the project duration?
Budget: Are the project finances within the competition scope?
Team: Is the organisation / delivery team credible in this technical area?

How we evaluate

Successful applicants will be invited to a pitch day, giving them a chance to meet the HMGCC Co- Creation team and pitch the proposal during a 20 minute presentation, followed by questions.
After the pitch day, a final funding decision will be made. For unsuccessful applicants, feedback will be given in a timely manner.

Invitation to present

Clarifying questions or general requests for assistance can be submitted directly to cocreation@hmgcc.gov.uk prior to the cut-off date. These clarifying questions may be technical, procedural, or commercial in subject, or anything else where assistance is required. Please note that answered questions will be published to facilitate a fair and open competition.

Clarifying questions

HMGCC Co-Creation are working with a multiple and diverse set of community collaborators to broadcast and host our challenges. <a href="https://www.hmgcc.gov.uk/co-creation/">Please follow this link for the full list of community collaborators.</a>
If possible, please submit applications via a community collaborator.
If the community collaborator does not host an application route, please send applications directly to cocreation@hmgcc.gov.uk, including the challenge title with a note of the community collaborator where this challenge was first viewed.
All information you provide to us as part of your proposal, whether submitted directly or via a collaborator platform, will be handled in confidence.

Routes to apply

Applications must be no more than six pages or six slides in length. The page/slide limit excludes personnel CVs and organisational profiles.
There is no prescribed application format, however, please ensure your application includes the following:
Applicant details: Contact name, organisation details and registration number.
Scope: Describe how the project aligns to the challenge scope.
Innovation: Describe the innovation and technology intended to be delivered in the project, along with new IP that will be generated or existing IP that can be used
Deliverables: Describe the project outcomes and their impacts.
Timescale: Detail how a <a href="https://www.gartner.com/en/marketing/glossary/minimum-viable-product-mvp-">minimum viable product</a> will be achieved within the project duration.
Budget: Provide project finances against deliverables within the project duration.
Team: Key personnel CVs and expertise, organisational profile if applicable.

How to apply

Proposals must be compliant with the HMGCC Co-Creation terms and conditions; by submitting your proposal you are confirming your organisation&rsquo;s unqualified acceptance of <a href="https://iuk.ktn-uk.org/wp-content/uploads/2024/07/HMGCC-Terms-Conditions.pdf">Co-Creation terms and conditions</a>.
Commercial contracts and funding of successful applications will be engaged via our commercial collaborator, Cranfield University.&nbsp;

Co-Creation terms and conditions

<a href="https://www.hmgcc.gov.uk">HMGCC</a> work with the national security community, UK government, academia, private sector partners and international allies to bring engineering ingenuity to the national security mission, creating tools and technologies that drive us ahead and help to protect the nation.
<a href="https://www.hmgcc.gov.uk/co-creation/">HMGCC Co-Creation</a> is a partnership between <a href="https://www.hmgcc.gov.uk">HMGCC</a> and <a href="https://www.gov.uk/government/organisations/defence-science-and-technology-laboratory">Dstl</a> (Defence Science and Technology Laboratory), created to deliver a new, bold and innovative way of working with the wider UK science and technology community. We bring together the best in class across industry, academia, and government, to work collaboratively on national security engineering challenges and accelerate innovation.
HMGCC Co-Creation is part of the <a href="https://www.gov.uk/government/organisations/national-security-technology-and-innovation-exchange">NSTIx</a> Co-Creation network, which enable the UK government national security community to collaborate on science, technology and innovation activities and to deliver these in partnership with a more diverse set of contributors for greater shared impact and pace.
HMGCC Co-Creation aim to work collaboratively with the successful solution providers by utilising in-house delivery managers working <a href="https://www.gov.uk/service-manual/agile-delivery/agile-methodologies">Agile</a> by default. This process will involve access to HMGCC Co-Creation's technical expertise and facilities to bring a product to market more effectively than traditional customer-supplier relationships.

HMGCC Co-Creation supporting information

Who owns the intellectual property?
As per the HMGCC Co-Creation terms and conditions, project IP shall belong exclusively to the solution provider, granting the Authority a non-exclusive, royalty free licence.
Who are the end customers?
National security users. This is a wide range of different UK government departments which will vary from challenge to challenge. This is a modest market and so we would encourage solution providers to consider dual use and commercial exploitation.
What funding is eligible?
This is not grant funding, so HMGCC Co-Creation funds all time, materials, overheads and indirect costs.
How many projects are funded for each challenge?
On average we fund two solution providers per challenge, but it does come down to the merit and strength of the received proposals.
Do you expect to get a full product by the end of the funding?
It changes from challenge to challenge, but it&rsquo;s unlikely. We typically see this initial funding as a feasibility or prototyping activity.
Is there the possibility for follow-on funding beyond project timescale?
If the solution delivered by the end of the project is judged by the HMGCC Co-Creation team as feasible, viable and desirable, then phase 2 funding may be made available.
Can we collaborate with other organisations to form a consortium?
Yes, multi-disciplinary consortiums are encouraged. But please note there are budget restrictions outlined in key information, depending on the challenge there are sometimes higher budgets made available for consortiums.
What are the vetting / security clearances requirement to work with HMGCC Co- Creation?
Our preference is all work to be conducted at <a href="https://www.gov.uk/government/publications/government-security-classifications/government-security-classifications-policy-html">OFFICIAL</a>. As default there is no vetting or security clearance requirement prior to contract award, we may however ask during the course of the project that personnel undertaking work complete <a href="https://www.gov.uk/government/publications/united-kingdom-security-vetting-clearance-levels/national-security-vetting-clearance-levels">BPSS</a> vetting or equivalent, which HMGCC Co-Creation will sponsor.
We think we have already solved this challenge,can we still apply?
That would be welcomed. If your product fits our needs, then we would like to hear.
Can you explain the Technology Readiness Level (TRL)?
Please see the <a href="https://www.ukri.org/councils/stfc/guidance-for-applicants/check-if-youre-eligible-for-funding/eligibility-of-technology-readiness-levels-trl/">UKRI</a> definition for further detail. Can I source components from the list of restricted countries, e.g. electronic components?
Yes, that is acceptable under phase 1 - feasibility, as long as it doesn&rsquo;t break <a href="https://www.gov.uk/guidance/current-arms-embargoes-and-other-restrictions">UK government trade restrictions and/or arms embargoes</a>.

FAQs

Solution providers should also consider their business development and supply chains are in-line with the <a href="https://www.gov.uk/government/publications/national-security-and-investment-act-guidance-on-notifiable-acquisitions/national-security-and-investment-act-guidance-on-notifiable-acquisitions">National Security and Investment Act</a>, NPSA <a href="https://www.npsa.gov.uk/trusted-research">trusted research</a> and <a href="https://www.npsa.gov.uk/secure-innovation/company-guidance">secure innovation</a> advice.
Advice and guidance on how to keep your organisation secure online can also be found through the <a href="https://www.ncsc.gov.uk/section/advice-guidance/all-topics">National Cyber Security Centre</a>.

Further considerations

The competition talks about imaging PCBs in the range of visible and x-ray light. Would the Authority consider approaches that use longer wavelengths of electromagnetic energy under this challenge?&nbsp;
There is no restriction on the wavelengths to use to image PCBs and the solution can include multispectral imaging, provided it can be done safely. The solution to imaging should include a method to image the internal copper traces of the PCB.&nbsp;
&nbsp;
Is the use of ML vision processing in solutions considered mandatory?&nbsp;
The use of ML is not mandatory, all valid approaches to interpreting the images are encouraged and assessed equally.&nbsp;
&nbsp;
Do we have access to any data / circuit boards / CT scanners / X ray machines, or do we have to source everything ourselves?&nbsp;
CT radiograph and reconstruction volume data of a small number of PCBs can be provided. Commercial PCBs with open source design data are also available.&nbsp;
&nbsp;
Can we build a computer model in unity to show how this would work in practice or do you need a physical PoC?&nbsp;
Could you explain more about what you are thinking with building a computer model in unity? Ideally would like a PoC, though we don&rsquo;t understand enough about the unity approach to give a definitive answer.&nbsp;
&nbsp;
Is 80k the limit for this work?&nbsp;
For this phase yes. At the end of the phase the work completed will be reviewed against existing budget allocations. So there is potential for further funding at a later date.&nbsp;
&nbsp;
Can we use off the shelf data processing programs like FME, Hadoop, MATLAB or do we have to build it all from scratch?&nbsp;
In the final application, data processing will preferably be done off-line. While there are no limitations to which data processing approach to use, being able to run it off-line will be of benefit.&nbsp;
&nbsp;
Is there anything we&rsquo;re not allowed to use?&nbsp;
I would like to leave the solution open to not constrain creative ideas. Please feel free to ask about anything you think might fall into this category of not allowed.&nbsp;
&nbsp;
Do we have test data or test items we know are tempered or are not tampered to use as QA for the design process.&nbsp;
A small set of CT data and gerber manufacturing data for tampered/not tampered PCBs can be provided, though other options should be explored first.&nbsp;
&nbsp;
What datasets are available for AI modelling? As this is a key limiting factor within the tight delivery timeframes to developing a sophisticated AI. EG, are there datasets of PCB Xray/CT images linked to CAD files? And if so, what's the rough size of the available data (in terms of number of samples)?&nbsp;
We will not be providing large datasets for AI training purposes, however a small set of CT data and gerber manufacturing data for tampered/not tampered PCBs can be provided.&nbsp;
&nbsp;
If no datasets are available, this presents an opportunity to deploy a novel imaging technology that we've been developing (redacted). We believe this technology (redacted) has particular relevance for establishing the integrity of copper tracks on a pcb, but the lack of existing datasets poses a concern for success AI development. Nonetheless, we believe we could develop a demonstrator in the timeframes, but this would be on non-populated PCBs (with further work then required to upgrade the solution to work on populated PCBs). Would this be an acceptable end point for the project?&nbsp;
Tracing of copper tracks and their attribution across multi-layered PCBs with a development pathway of how this can be applied to populated PCBs to overcome problems should as &lsquo;shadowing&rsquo; is of interest.&nbsp;
&nbsp;
What are the dimensions and thickness of the PCB board?&nbsp;
PCB dimensions could be up to 30cm by 20 cm, more likely smaller 15cm x 10 cm. Thickness up to 2mm but more likely 1mm to 1.5mm.&nbsp;
&nbsp;
Which types of X-Ray technology or machines have been attempted?&nbsp;
Micro-focus CT scanning up to 200KeV.&nbsp;
&nbsp;
What were the limitations of the existing X-ray technology that was used?&nbsp;
Component&rsquo;s metal artefacts &ldquo;shadow&rdquo; images, high barrier to entry on machine cost and user training. Can be difficult to manually interpret volume.&nbsp;
&nbsp;
What is the minimum size of the copper traces that can be analysed?&nbsp;
Each copper trace could be less than 35um in height, less than 100um in width and a copper clad layer less than 150um thick.&nbsp;
&nbsp;
How many copper layers are typically found in an assembly, and what is the maximum number observed?&nbsp;
A PCB for verification could consist of multiple (potentially 10 or more) layers of copper traces, bonded on to FR4 glass epoxy substrates and laminated together.&nbsp;
&nbsp;
What is the closest dielectric separation between copper layers?&nbsp;
Pre-preg thickness between layers minimum would be 50um though likely to be 100um.&nbsp;
&nbsp;
Where are the copper traces located within the PCB board?&nbsp;
Traces would be on layers spread through out the PCB stack up. Some layers will be planes of copper for power and ground low impedance distribution, while other layers will be signal layers with mostly copper traces surrounded copper planes of power and ground for signal and power integrity.&nbsp;
&nbsp;
While the goal is to focus on an image-based solution can some limited probing take place?&nbsp;
Absolutely, the goal is to determine the tracking layout and if probing benefits the solution understanding then yes.&nbsp;
&nbsp;
Would we be able to power the PCB board under test?&nbsp;
Yes&nbsp;
&nbsp;
Is there an expected limit to the cost of the final system once production ready?&nbsp;
No cost is currently defined to not constrain potential solutions. It is envisaged the system would be R&amp;D lab equipment scale.&nbsp;

Assurance of printed circuit boards using machine vision

Opportunity

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